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GC3
This is a work in progress. (Started May 12).
What GC3 is:
GC3 is NickGuggemos's third attempt to design a CPU that he might reasonably be able to build from off-the-shelf electronics.
GC3 differs from GC1 and GC2 primarily in the design of the control section of the CPU. Whereas GC1 and GC2 used shift registers and asynchronous logic to control the various components of the processor, the design of GC3 uses a microcode system.
GC3 Overview
GC3 has a number of sections including the ALU, memory interface, programmer-visible register set, intraprocessor bus, and control section. Each section of the cpu has a number of inputs to control what it does. A simple register might only have two such control inputs; one that causes it to latch data from the intraprocessor bus and one that causes it to output data to the intraprocessor bus. In general, the control inputs to a section will cause the section to preform one of three operations: latching data from the intraprocessor bus, outputting data to the intraprocessor bus, and operating on internal state. Latch controls are edge triggered, output and operation controls are level triggered. Each control input is driven by a control line, which, in turn, is driven by the control section. All control lines are updated simultaneously.
GC3 Microcode:
The control section of the GC3 is very simple, yet very flexible; It consists of EEPROM, a counter, two latches, and a register. The data stored in the EEPROM represents GC3 Microcode. Each bit of the the EEPROM word represents a control line. As a consequence, data stored in the EEPROM can be directly output to the control lines--almost. The two latchs form a two stage, parallel, output buffer between the EEPROM and the control lines, as detail which will be explained later.
The output of the control section's counter and register are concatenated to form an address, which is used by the EEPROM to select a word (bitpattern) to output the the buffer. The counter is incremented each cycle, so a new pattern is available to the buffer each cycle. GC3 is run by outputing appropriate data from the EEPROM in sequence.
The GC3's microcode can implement a GC1- or GC2-like interface, or it may implement another interface.
If there were sufficent buses and control bits, each section could be multiported, thus allowing very complex, parallel operations to be executed.
CPU contents:
The CPU will have an arithmetic and logic unit, a set of registers, an interface to memory, and a control section.
==Instructions==
